1. Field of the Invention
The invention relates to an amplifier output stage designed to be made in integrated circuit form.
To supply high currents to a load, whether it be a resistive load, a capacitive load or a combined load, without working with a high rest current, push-pull output stages are most often used.
2. Description of the Prior Art
A push-pull stage comprises two main transistors placed in series between a positive supply terminal and a negative supply terminal. One of the transistors supplies the current during the positive half-waves and the other transistor supplies the current during the negative half-waves.
The junction point of the transistors constitutes the output of the stage. The load is connected between this output and a reference terminal which is at an intermediate potential between that of the two supply terminals.
In the most conventional type of push-pull stage (FIG. 1), the transistor T1 connected to the positive supply terminal is of the NPN type, and the other transistor, T2, is of the PNP type. The emitters are connected to the output S and the bases are connected to the input E. The rest current, namely the current that goes through the transistors when the output voltage is zero, may be low or even zero.
However, in monolithic integration techniques, it is preferred not to use any PNP transistors. They are bulky and low-speed elements. And it is also preferred not to use other technologies that mix, for example, bipolar transistors and field-effect transistors. Firstly, this considerably complicates the technology and, secondly, the performance characteristics of the stage will be unfavorably affected as far as speed is concerned, for field-effect transistors have capacitances that greatly slow down the electrical signals.
It has therefore been proposed to make push-pull type stages that use only NPN transistors. An example thereof is given is FIG. 2. This stage has two output transistors T1 and T2 capable of giving high currents to a load Z, these two transistors being in series between the positive and negative supply terminals, their junction point constituting the output S to which the load Z is connected. One of the transistors supplies the outgoing current flowing towards the load (positive half-waves), while the other transistor supplies the incoming current from the load (negative half-waves). A third transistor T3 controls the first two transistors: the bases of the first two transistors are respectively connected to the collector and to the emitter of the third transistor. The input E of the stage is the base of the third transistor: this third transistor is biased with an emitter resistance and a collector resistance.
This output stage is better suited to monolithic integration because it has only NPN transistors. Only one technology (NPN bipolar technology) is needed. It furthermore benefits from the speed of the NPN bipolar technology. However, it has poor linearity. It can hardly be used except as an auxiliary amplifier in a looped system (where the looping provides for the linearity). At the same time, when it is used in this way, it can be used only at fairly low frequencies, and the advantage that might be derived from the use of an entirely NPN technology is therefore lost.